The present invention relates generally to integrated circuit (IC) designs, and more particularly to bipolar devices with a thin-body structure. This concept of this patent application can be referred to merged MOS/bipolar device in US patent publication No. 2006/0197185 and No. 2007/0105301.
Although complementary metal-oxide-semiconductor (CMOS) devices have advantages of low power consumption and high input impedance, they often need some specially designed I/O devices and circuits to protect them from high voltage signals. Those I/O devices and circuits usually require extra masks in the course of semiconductor processing. One way to simplify the semiconductor processing is to use bipolar devices as the I/O devices. The bipolar devices are able to sustain relatively high voltage. In addition, bipolar devices have many advantages over CMOS devices in designing analog circuitry. However, the conventional bipolar device is very complicated to manufacture. Though parasitic lateral bipolar devices can be formed through standard CMOS process, their performance is generally inferior to those formed by genuine bipolar processes. It would be desirable to design high performance bipolar devices in CMOS compatible process to achieve better performance.
FIG. 1 illustrates a conventional PNP bipolar transistor 10 compatible with CMOS process technologies. The LOCal Oxidation of Silicon (LOCOS) isolations 11 define three active areas 12, 13 and 14 on N well 15 in a semiconductor substrate. The active areas 12 and 13 doped with P-type impurities form an emitter 16 and a collector 17, respectively. The LOCOS isolation 11 between the emitter 16 and collector 17 defines an intrinsic base 18 thereunder in the Nwell 15. An extrinsic base 19 is electrically connected to the intrinsic base 18 via the body of the Nwell 15. The extrinsic base 19 is doped with N-type impurities to improve its conductivity. When the emitter 16, collector 17 and extrinsic base 19 are properly biased, carriers would flow between the emitter 16 and the collector 17 to produce amplification of currents.
The design of the conventional PNP bipolar transistor 10 is not suitable for ICs using three-dimensional CMOS devices. As the size of electronic devices in ICs continues to scale down, the IC design and manufacturing face new challenges. For example, failure caused by punch-though between the source and the drain of a CMOS device becomes a serious reliability issue to CMOS devices with a scale under 45 nm. As a result, many new designs have been proposed to improve the reliability of CMOS devices scaled under 45 nm. One of the proposed designs is the Fin Field Effect Transistor (FinFET) characterized by its fin-shaped source and drain, and a surrounding gate structure. The width of the fin-shaped source and drain can be controlled to eliminate the punch-through often occurred between the source and the drain of a conventional CMOS device.
As such, what is desired is a FinFET-like bipolar device that can be formed by regular CMOS process.